The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas kerja ini, struktur baharu litar Voltan-Mod MAX-MIN dibentangkan untuk sistem tak linear, aplikasi kabur, rangkaian saraf dan lain-lain. Pasangan pembezaan dengan cermin arus cascode yang dipertingkat digunakan untuk memilih input yang diingini. Kelebihan struktur yang dicadangkan ialah kekerapan operasi yang tinggi, ketepatan tinggi, penggunaan kuasa yang rendah, kawasan yang rendah dan pengembangan mudah untuk berbilang input dengan menambah hanya tiga transistor untuk setiap input tambahan. Litar yang dicadangkan yang disimulasikan oleh HSPICE dalam proses CMOS 0.35 µm menunjukkan jumlah penggunaan kuasa sebanyak 85 µW dalam frekuensi operasi 5 MHz daripada satu bekalan 3.3-V. Juga, jumlah luas litar yang dicadangkan adalah kira-kira 420 µm2 untuk dua voltan masukan, dan akan dinaikkan sedikit untuk setiap input tambahan.
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Salinan
Mohammad SOLEIMANI, Abdollah KHOEI, Khayrollah HADIDI, Vahid Fagih DINAVARI, "Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3044-3051, December 2009, doi: 10.1587/transfun.E92.A.3044.
Abstract: In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3044/_p
Salinan
@ARTICLE{e92-a_12_3044,
author={Mohammad SOLEIMANI, Abdollah KHOEI, Khayrollah HADIDI, Vahid Fagih DINAVARI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption},
year={2009},
volume={E92-A},
number={12},
pages={3044-3051},
abstract={In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.},
keywords={},
doi={10.1587/transfun.E92.A.3044},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3044
EP - 3051
AU - Mohammad SOLEIMANI
AU - Abdollah KHOEI
AU - Khayrollah HADIDI
AU - Vahid Fagih DINAVARI
PY - 2009
DO - 10.1587/transfun.E92.A.3044
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.
ER -