The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Penyelidikan mengenai meramal dan mengalihkan titik panas litografi telah berleluasa dalam industri semikonduktor baru-baru ini, dan dikenali sebagai salah satu cabaran paling sukar untuk mencapai liputan pengesanan berkualiti tinggi. Untuk menyediakan pelaksanaan reka bentuk fizikal dengan nikmat pereka dalam menetapkan titik panas, dalam kertas kerja ini, kami membentangkan kaedah pengesanan titik panas yang mulia dan tepat, yang dipanggil "merata dan pemarkahan" algoritma berdasarkan gabungan wajaran parameter kualiti imej (iaitu, cerun log imej ternormal (NILS), faktor peningkatan ralat topeng (MEEF), dan kedalaman fokus (DOF)) daripada simulasi litografi. Dalam algoritma kami, pertama, panas- fungsi pemarkahan tempat mengambil kira tahap keterukan ditentukur dengan kelayakan tetingkap proses, dan kemudian kaedah regresi kuasa dua terkecil digunakan untuk menentukur pekali pemberat bagi setiap parameter kualiti imej Dengan cara ini, selepas kami memperoleh fungsi pemarkahan dengan hasil wafer, kaedah kami boleh digunakan pada reka bentuk masa hadapan menggunakan proses yang sama Dengan menggunakan fungsi pemarkahan yang ditentukur ini, kami berjaya menjana panduan dan peraturan penetapan untuk mengesan kawasan titik panas dengan mencari nilai bias tepi yang membawa kepada tahap skor bebas titik panas menyepadukan maklumat panduan penetapan titik panas ke dalam penyunting reka letak untuk memudahkan persekitaran reka bentuk yang menguntungkan pengguna Dengan menggunakan kaedah kami pada peranti memori 60 nm nod dan ke bawah, kami boleh berjaya mencapai margin tetingkap proses yang mencukupi untuk menghasilkan pengeluaran besar-besaran.
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Salinan
Yonghee PARK, Junghoe CHOI, Jisuk HONG, Sanghoon LEE, Moonhyun YOO, Jundong CHO, "Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3082-3085, December 2009, doi: 10.1587/transfun.E92.A.3082.
Abstract: The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3082/_p
Salinan
@ARTICLE{e92-a_12_3082,
author={Yonghee PARK, Junghoe CHOI, Jisuk HONG, Sanghoon LEE, Moonhyun YOO, Jundong CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation},
year={2009},
volume={E92-A},
number={12},
pages={3082-3085},
abstract={The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.},
keywords={},
doi={10.1587/transfun.E92.A.3082},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3082
EP - 3085
AU - Yonghee PARK
AU - Junghoe CHOI
AU - Jisuk HONG
AU - Sanghoon LEE
AU - Moonhyun YOO
AU - Jundong CHO
PY - 2009
DO - 10.1587/transfun.E92.A.3082
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.
ER -