The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas kerja ini, seni bina penapis penyahsekatan yang sangat selari untuk H.264/AVC dicadangkan untuk memproses satu sekatan makro dalam 48 kitaran jam dan memberikan sokongan masa nyata kepada jujukan QFHD@60 fps pada kurang daripada 100 MHz. 4 penapis tepi disusun dalam 2 kumpulan untuk pemprosesan serentak tepi menegak dan mendatar digunakan dalam seni bina ini untuk meningkatkan daya pemprosesannya. Walaupun keselarian meningkat, bahaya saluran paip timbul disebabkan kependaman penapis tepi dan pergantungan data algoritma nyahsekat. Untuk menyelesaikan masalah ini, jadual pemprosesan zig-zag dicadangkan untuk menghapuskan gelembung saluran paip. Laluan data seni bina kemudiannya diperolehi mengikut jadual pemprosesan dan dioptimumkan melalui penggabungan aliran data, untuk meminimumkan kos logik dan penimbal dalaman. Sementara itu, kadar input data seni bina direka bentuk untuk sama dengan daya pemprosesannya, manakala susunan penghantaran data input juga boleh sepadan dengan jadual pemprosesan zig-zag. Oleh itu, tiada penimbal interkomunikasi diperlukan antara penapis nyahsekat dan komponen sebelumnya untuk pemadanan kelajuan atau penyusunan semula data. Akibatnya, hanya satu 24
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Salinan
Dajiang ZHOU, Jinjia ZHOU, Jiayi ZHU, Satoshi GOTO, "A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3203-3210, December 2009, doi: 10.1587/transfun.E92.A.3203.
Abstract: In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3203/_p
Salinan
@ARTICLE{e92-a_12_3203,
author={Dajiang ZHOU, Jinjia ZHOU, Jiayi ZHU, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications},
year={2009},
volume={E92-A},
number={12},
pages={3203-3210},
abstract={In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24
keywords={},
doi={10.1587/transfun.E92.A.3203},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3203
EP - 3210
AU - Dajiang ZHOU
AU - Jinjia ZHOU
AU - Jiayi ZHU
AU - Satoshi GOTO
PY - 2009
DO - 10.1587/transfun.E92.A.3203
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24
ER -