The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Beberapa masalah dalam reka bentuk sistem ukuran jitter terbina dalam (BIJM) telah dikenal pasti sejak beberapa tahun kebelakangan ini. Masalahnya dikaitkan dengan jam pensampelan jitter rendah luaran, kawasan cip, resolusi pemasaan atau julat pengukuran melalui kesan variasi suhu voltan proses (PVT). Dalam kerja ini, terdapat tiga cadangan pendekatan dan satu kaedah konvensional yang menambah baik sistem BIJM. Untuk tahap sistem, teknik pensampelan isyarat setara sebenar yang dicadangkan digunakan untuk mengosongkan keperluan jam pensampelan jitter rendah luaran. Struktur angkup Vernier yang dicadangkan digunakan untuk mengurangkan kos kawasan cip untuk resolusi pemasaan yang ditetapkan. Pada peringkat litar, teknik fokus auto yang dicadangkan menghapuskan kesan variasi PVT untuk julat ukuran. Teknik imbasan melangkah adalah kaedah konvensional yang digunakan untuk meminimumkan kos kawasan litar kaunter. Kesemua teknik ini telah dilaksanakan dalam proses CMOS 0.35 µm. Tambahan pula, teknik ini berjaya disahkan dalam resolusi litar 14 ps dan kawasan cip 500*750 µm untuk julat ukuran 100-400 MHz.
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Salinan
Shu-Yu JIANG, Chan-Wei HUANG, Yu-Lung LO, Kuo-Hsing CHENG, "Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 389-400, February 2009, doi: 10.1587/transfun.E92.A.389.
Abstract: Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.389/_p
Salinan
@ARTICLE{e92-a_2_389,
author={Shu-Yu JIANG, Chan-Wei HUANG, Yu-Lung LO, Kuo-Hsing CHENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System},
year={2009},
volume={E92-A},
number={2},
pages={389-400},
abstract={Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.},
keywords={},
doi={10.1587/transfun.E92.A.389},
ISSN={1745-1337},
month={February},}
Salinan
TY - JOUR
TI - Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 389
EP - 400
AU - Shu-Yu JIANG
AU - Chan-Wei HUANG
AU - Yu-Lung LO
AU - Kuo-Hsing CHENG
PY - 2009
DO - 10.1587/transfun.E92.A.389
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.
ER -