The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan seni bina NoC hierarki untuk menyokong isyarat GT (Guaranteed Throughput) untuk memproses data multimedia dalam sistem terbenam. Seni bina menyediakan persekitaran komunikasi yang memenuhi pelbagai syarat kekangan komunikasi di kalangan IP dalam kuasa dan kawasan. Dengan sistem berdasarkan pensuisan paket, yang memerlukan litar storan/kawalan untuk menyokong isyarat GT, adalah sukar untuk memenuhi kekangan reka bentuk dalam kawasan, kebolehskalaan dan penggunaan kuasa. Kertas ini mencadangkan hierarki 4
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Salinan
Woo Joo KIM, Sung Hee LEE, Sun Young HWANG, "Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 3, pp. 890-899, March 2009, doi: 10.1587/transfun.E92.A.890.
Abstract: This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia data in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 4
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.890/_p
Salinan
@ARTICLE{e92-a_3_890,
author={Woo Joo KIM, Sung Hee LEE, Sun Young HWANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching},
year={2009},
volume={E92-A},
number={3},
pages={890-899},
abstract={This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia data in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 4
keywords={},
doi={10.1587/transfun.E92.A.890},
ISSN={1745-1337},
month={March},}
Salinan
TY - JOUR
TI - Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 890
EP - 899
AU - Woo Joo KIM
AU - Sung Hee LEE
AU - Sun Young HWANG
PY - 2009
DO - 10.1587/transfun.E92.A.890
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2009
AB - This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia data in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 4
ER -