The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Keselamatan tangkapan, (ditakrifkan sebagai pengelakan ralat pemasaan akibat aktiviti pensuisan pelancaran yang terlalu tinggi dalam mod tangkapan semasa ujian imbasan pada kelajuan), adalah penting dalam mengelakkan kehilangan hasil akibat ujian. Walaupun beberapa teknik canggih tersedia untuk mengurangkan penurunan IR tangkapan, terdapat beberapa aliran penjanaan ujian selamat tangkapan yang lengkap. Kertas kerja ini menangani masalah dengan mencadangkan aliran penjanaan ujian tangkap-selamat yang baru dan praktikal, yang menampilkan (1) aliran penjanaan ujian tangkap-selamat yang lengkap; (2) pemeriksaan keselamatan tangkapan yang boleh dipercayai; dan (3) penambahbaikan tangkapan-keselamatan yang berkesan dengan menggabungkan X-pengenalan bit & X-mengisi dengan penjanaan ujian pelancaran-penukaran-aktiviti yang rendah. Aliran yang dicadangkan meminimumkan inflasi data ujian dan serasi dengan aliran penjanaan corak ujian automatik (ATPG) sedia ada. Teknik-teknik yang dicadangkan dalam aliran mencapai keselamatan tangkapan tanpa mengubah litar dalam ujian atau skema jam.
Kohei MIYASE
Xiaoqing WEN
Seiji KAJIHARA
Yuta YAMATO
Atsushi TAKASHIMA
Hiroshi FURUKAWA
Kenji NODA
Hideaki ITO
Kazumi HATAYAMA
Takashi AIKYO
Kewal K. SALUJA
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Salinan
Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA, Yuta YAMATO, Atsushi TAKASHIMA, Hiroshi FURUKAWA, Kenji NODA, Hideaki ITO, Kazumi HATAYAMA, Takashi AIKYO, Kewal K. SALUJA, "A Study of Capture-Safe Test Generation Flow for At-Speed Testing" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1309-1318, July 2010, doi: 10.1587/transfun.E93.A.1309.
Abstract: Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1309/_p
Salinan
@ARTICLE{e93-a_7_1309,
author={Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA, Yuta YAMATO, Atsushi TAKASHIMA, Hiroshi FURUKAWA, Kenji NODA, Hideaki ITO, Kazumi HATAYAMA, Takashi AIKYO, Kewal K. SALUJA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Study of Capture-Safe Test Generation Flow for At-Speed Testing},
year={2010},
volume={E93-A},
number={7},
pages={1309-1318},
abstract={Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.},
keywords={},
doi={10.1587/transfun.E93.A.1309},
ISSN={1745-1337},
month={July},}
Salinan
TY - JOUR
TI - A Study of Capture-Safe Test Generation Flow for At-Speed Testing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1309
EP - 1318
AU - Kohei MIYASE
AU - Xiaoqing WEN
AU - Seiji KAJIHARA
AU - Yuta YAMATO
AU - Atsushi TAKASHIMA
AU - Hiroshi FURUKAWA
AU - Kenji NODA
AU - Hideaki ITO
AU - Kazumi HATAYAMA
AU - Takashi AIKYO
AU - Kewal K. SALUJA
PY - 2010
DO - 10.1587/transfun.E93.A.1309
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.
ER -