The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami memperincikan tatasusunan get boleh atur cara medan segerak sendiri (SSFPGA) dengan seni bina dwi-saluran paip (DP) untuk menyembunyikan masa pra-cas untuk logik dinamik, dan pengoptimuman daya pemprosesannya dengan menggunakan penjajaran saluran paip yang dilaksanakan pada litar penanda aras. LUT segerak sendiri (SSLUT) terdiri daripada tiga struktur jenis pokok input dengan 8 bit SRAM untuk pengaturcaraan. Kotak suis segerak sendiri (SSSB) terdiri daripada kedua-dua transistor pas dan penampan kepada isyarat laluan, dengan 12 bit SRAM. Satu blok biasa dengan satu SSLUT dan satu SSSB menduduki 2.2 Mλ2 kawasan dengan 35 bit SRAM, dan prototaip SSFPGA dengan 34
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Salinan
Benjamin STEFAN DEVLIN, Toru NAKURA, Makoto IKEDA, Kunihiro ASADA, "A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1319-1328, July 2010, doi: 10.1587/transfun.E93.A.1319.
Abstract: We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 34
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1319/_p
Salinan
@ARTICLE{e93-a_7_1319,
author={Benjamin STEFAN DEVLIN, Toru NAKURA, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment},
year={2010},
volume={E93-A},
number={7},
pages={1319-1328},
abstract={We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 34
keywords={},
doi={10.1587/transfun.E93.A.1319},
ISSN={1745-1337},
month={July},}
Salinan
TY - JOUR
TI - A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1319
EP - 1328
AU - Benjamin STEFAN DEVLIN
AU - Toru NAKURA
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2010
DO - 10.1587/transfun.E93.A.1319
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 34
ER -