The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam makalah ini, seni bina VLSI penyahkod parameter bersama dicadangkan untuk merealisasikan pengiraan vektor gerakan (MV), mod ramalan intra (IPM) dan kekuatan sempadan (BS) untuk aplikasi H.264/AVC definisi ultra tinggi. Untuk seni bina ini, saluran paip 64-kitaran-setiap-MB dengan mod kawalan dipermudahkan direka bentuk untuk meningkatkan daya pemprosesan sistem dan mengurangkan kos perkakasan. Selain itu, untuk menjimatkan lebar jalur ingatan, data yang merangkumi maklumat gerakan untuk gambar yang terletak bersama dan baris terakhir dinyahkod, dipraproses sebelum disimpan ke DRAM. Format storan berasaskan partition digunakan untuk memekatkan data tahap MB, manakala kaedah mampatan berdasarkan pengekodan panjang berubah digunakan untuk mengurangkan saiz data dalam setiap partition. Keputusan percubaan menunjukkan reka bentuk kami mampu 3840 masa nyata
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Salinan
Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, "A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 8, pp. 1425-1433, August 2010, doi: 10.1587/transfun.E93.A.1425.
Abstract: In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1425/_p
Salinan
@ARTICLE{e93-a_8_1425,
author={Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications},
year={2010},
volume={E93-A},
number={8},
pages={1425-1433},
abstract={In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
keywords={},
doi={10.1587/transfun.E93.A.1425},
ISSN={1745-1337},
month={August},}
Salinan
TY - JOUR
TI - A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1425
EP - 1433
AU - Jinjia ZHOU
AU - Dajiang ZHOU
AU - Xun HE
AU - Satoshi GOTO
PY - 2010
DO - 10.1587/transfun.E93.A.1425
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2010
AB - In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840
ER -