The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Sebagai salah satu langkah balas peringkat logik terhadap serangan DPA (Analisis Kuasa Berbeza), Random Switching Logic (RSL) telah dicadangkan oleh Suzuki, Saeki dan Ichikawa pada tahun 2004 . Teknik RSL telah digunakan pada perkakasan AES dan cip prototaip telah dilaksanakan dengan perpustakaan CMOS standard 0.13-µm untuk menilai rintangan DPA . Walaupun tujuan utama menggunakan RSL adalah untuk menentang serangan DPA, hasil percubaan kami Analisis Kerosakan berasaskan Jam (CFA) menunjukkan bahawa seseorang boleh mendedahkan maklumat rahsia daripada cip prototaip. Kertas kerja ini menerangkan mekanisme serangan CFA dan membincangkan sebab kejayaan serangan terhadap pelaksanaan prototaip AES dengan RSL (RSL-AES). Tambahan pula, kami mempertimbangkan pelaksanaan RSL-AES yang ideal yang menentang serangan CFA.
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Salinan
Kazuo SAKIYAMA, Kazuo OHTA, "On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 1, pp. 172-179, January 2010, doi: 10.1587/transfun.E93.A.172.
Abstract: As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.172/_p
Salinan
@ARTICLE{e93-a_1_172,
author={Kazuo SAKIYAMA, Kazuo OHTA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL},
year={2010},
volume={E93-A},
number={1},
pages={172-179},
abstract={As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.},
keywords={},
doi={10.1587/transfun.E93.A.172},
ISSN={1745-1337},
month={January},}
Salinan
TY - JOUR
TI - On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 172
EP - 179
AU - Kazuo SAKIYAMA
AU - Kazuo OHTA
PY - 2010
DO - 10.1587/transfun.E93.A.172
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2010
AB - As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.
ER -