The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Anggaran pergerakan saiz blok boleh ubah yang dibangunkan oleh standard pengekodan video terkini H.264/AVC ialah pendekatan yang cekap untuk mengurangkan lebihan sementara. Kerumitan pengiraan intensif yang datang daripada teknik saiz blok boleh ubah menjadikan pemecut berwayar keras penting, untuk aplikasi masa nyata. Sebarkan jumlah separa bagi perbezaan mutlak (Sebarkan Separa SAD) dan Pokok SEDIH enjin berwayar keras mengatasi prestasi rakan sejawat lain, terutamanya dengan mengambil kira kesan sokongan teknik saiz blok berubah-ubah. Dalam makalah ini, penulis menggunakan pendekatan peringkat seni bina dan peringkat litar untuk meningkatkan kekerapan operasi maksimum dan mengurangkan overhed perkakasan Sebarkan Separa SAD and Pokok SEDIH, manakala metrik lain, dari segi kependaman, lebar jalur memori dan penggunaan perkakasan, seni bina asal dikekalkan. Eksperimen menunjukkan bahawa dengan menggunakan pendekatan yang dicadangkan, pada frekuensi operasi 110.8 MHz, berbanding dengan seni bina asal, 14.7% dan 18.0% kiraan pintu boleh disimpan untuk Sebarkan Separa SAD and Pokok SEDIH, masing-masing. Dengan teknologi TSMC 0.18 µm 1P6M CMOS, yang dicadangkan Sebarkan Separa SAD seni bina mencapai frekuensi operasi 231.6 MHz dengan kos 84.1 k pintu. Sejajar dengan itu, kekerapan kerja maksimum yang dioptimumkan Pokok SEDIH seni bina dipertingkatkan kepada 204.8 MHz, iaitu hampir dua kali ganda daripada yang asal, manakala overhed perkakasannya hanyalah 88.5 k-gate.
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Salinan
Zhenyu LIU, Dongsheng WANG, Takeshi IKENAGA, "Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 11, pp. 2065-2073, November 2010, doi: 10.1587/transfun.E93.A.2065.
Abstract: Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2065/_p
Salinan
@ARTICLE{e93-a_11_2065,
author={Zhenyu LIU, Dongsheng WANG, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC},
year={2010},
volume={E93-A},
number={11},
pages={2065-2073},
abstract={Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.},
keywords={},
doi={10.1587/transfun.E93.A.2065},
ISSN={1745-1337},
month={November},}
Salinan
TY - JOUR
TI - Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2065
EP - 2073
AU - Zhenyu LIU
AU - Dongsheng WANG
AU - Takeshi IKENAGA
PY - 2010
DO - 10.1587/transfun.E93.A.2065
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2010
AB - Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.
ER -