The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini mencadangkan pemproses cekap tenaga yang boleh digunakan sebagai alternatif reka bentuk untuk pemproses penskalaan voltan dinamik (DVS) dalam reka bentuk sistem terbenam. Pemproses terdiri daripada berbilang teras PE (elemen pemprosesan) dan memori cache set-asosiatif terpilih. Teras PE mempunyai seni bina set arahan yang sama tetapi berbeza dalam kelajuan jam dan penggunaan tenaga. Hanya satu teras PE diaktifkan pada satu-satu masa dan teras PE yang lain dinyahaktifkan menggunakan teknik pengaman jam dan pengaman isyarat. Kelebihan utama ke atas pemproses DVS ialah overhed kecil untuk menukar prestasinya. Simulasi peringkat get menunjukkan bahawa pemproses kami boleh mengubah prestasinya dalam 1.5 mikrosaat dan melesap kira-kira 10 nano-joule manakala pemproses DVS konvensional memerlukan ratusan mikrosaat dan menghilangkan beberapa mikro-joule untuk peralihan prestasi. Ini memungkinkan untuk menggunakan pemproses berbilang prestasi kami pada banyak sistem masa nyata dan melaksanakan kawalan voltan dinamik yang lebih halus dan lebih canggih.
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Salinan
Tohru ISHIHARA, "A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2533-2541, December 2010, doi: 10.1587/transfun.E93.A.2533.
Abstract: This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2533/_p
Salinan
@ARTICLE{e93-a_12_2533,
author={Tohru ISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems},
year={2010},
volume={E93-A},
number={12},
pages={2533-2541},
abstract={This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.},
keywords={},
doi={10.1587/transfun.E93.A.2533},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2533
EP - 2541
AU - Tohru ISHIHARA
PY - 2010
DO - 10.1587/transfun.E93.A.2533
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.
ER -