The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam reka bentuk biasa SoC (System-on-Chip), arus puncak yang besar sering berlaku berhampiran masa tepi jam aktif kerana pensuisan agregat bagi sejumlah besar transistor. Bilangan transistor pensuisan agregat boleh dikurangkan jika reka bentuk SoC boleh menggunakan skema jam gabungan tepi pencetus naik dan turun berbanding satu tepi pencetus naik (turun) tulen. Dalam kertas kerja ini, kami mencadangkan teknik dan algoritma penetapan tepi pencetus jam yang boleh menetapkan sama ada kelebihan pencetus meningkat atau kelebihan pencetus jatuh kepada setiap jam bagi setiap teras IP bagi SoC/NoC berasaskan IP tertentu (Rangkaian pada- reka bentuk cip). Matlamat algoritma adalah untuk mengurangkan arus puncak reka bentuk. Teknik cadangan kami telah dilaksanakan sebagai sistem perisian. Sistem boleh menggunakan teknik LP untuk mencari penyelesaian optimum atau suboptimum dalam beberapa saat. Sistem ini juga boleh menggunakan teknik ILP untuk mencari penyelesaian yang optimum, tetapi teknik ILP tidak sesuai digunakan untuk menyelesaikan reka bentuk yang kompleks. Keputusan eksperimen menunjukkan bahawa algoritma kami boleh mengurangkan arus puncak sehingga 56.3%.
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Salinan
Tsung-Yi WU, Tzi-Wei KAO, How-Rern LIN, "Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2581-2589, December 2010, doi: 10.1587/transfun.E93.A.2581.
Abstract: In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2581/_p
Salinan
@ARTICLE{e93-a_12_2581,
author={Tsung-Yi WU, Tzi-Wei KAO, How-Rern LIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs},
year={2010},
volume={E93-A},
number={12},
pages={2581-2589},
abstract={In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.},
keywords={},
doi={10.1587/transfun.E93.A.2581},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2581
EP - 2589
AU - Tsung-Yi WU
AU - Tzi-Wei KAO
AU - How-Rern LIN
PY - 2010
DO - 10.1587/transfun.E93.A.2581
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
ER -