The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam makalah ini, transceiver CMOS 8-jalur 130 nm mod cip tunggal termasuk penukar A/D/A dan penapis digital dengan antara muka LVDS 312 MHz dibentangkan. Untuk rantai pemancar, seni bina modulasi kuadratur langsung linear diperkenalkan untuk kedua-dua W-CDMA/HSDPA (Akses Paket Uplink Berkelajuan Tinggi) dan untuk GSM/EDGE. LPF jalur asas analog dan modulator kuadratur biasanya digunakan untuk GSM dan untuk EDGE. Untuk rantaian penerima penukaran langsung, blok ABB (Analog Base-Band), iaitu, LPF dan VGA, penukar A/D delta-sigma dan penapis FIR biasanya digunakan untuk W-CDMA/HSDPA (Akses Paket Pautan Bawah Berkelajuan Tinggi) dan GSM/EDGE untuk mengurangkan kawasan cip. Ciri-ciri mereka boleh dikonfigurasikan semula oleh urutan kawalan berasaskan daftar. Rantaian penerima juga termasuk pembatal offset DC berkelajuan tinggi dalam analog dan dalam peringkat digital, dan pengawal AGC serba lengkap, yang parameternya seperti pemalar masa boleh diprogramkan untuk bebas daripada kawalan DBB (Jalur Pangkalan Digital). Transceiver juga termasuk VCO jarak lebar dan PLL pecahan, pemacu dan penerima LVDS untuk antara muka digital berkelajuan tinggi 312 MHz. Keputusan yang diukur mendedahkan bahawa transceiver memenuhi spesifikasi 3GPP untuk W-CDMA/HSPA (Akses Paket Berkelajuan Tinggi) dan GSM/EDGE.
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Salinan
Hiroshi YOSHIDA, Takehiko TOYODA, Hiroshi TSURUMI, Nobuyuki ITOH, "A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 375-381, February 2010, doi: 10.1587/transfun.E93.A.375.
Abstract: In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.375/_p
Salinan
@ARTICLE{e93-a_2_375,
author={Hiroshi YOSHIDA, Takehiko TOYODA, Hiroshi TSURUMI, Nobuyuki ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface},
year={2010},
volume={E93-A},
number={2},
pages={375-381},
abstract={In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.},
keywords={},
doi={10.1587/transfun.E93.A.375},
ISSN={1745-1337},
month={February},}
Salinan
TY - JOUR
TI - A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 375
EP - 381
AU - Hiroshi YOSHIDA
AU - Takehiko TOYODA
AU - Hiroshi TSURUMI
AU - Nobuyuki ITOH
PY - 2010
DO - 10.1587/transfun.E93.A.375
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.
ER -