The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan penukar DC-DC injak/turun dengan tiga mod operasi untuk mencapai kecekapan tinggi dan voltan riak keluaran kecil. Mod peningkatan masa yang berterusan, yang dimasukkan antara mod wang dan mod rangsangan, dicadangkan untuk mencapai peralihan yang lancar. Dengan mod yang dicadangkan, voltan riak keluaran dikurangkan dengan ketara apabila voltan masukan adalah lebih kurang voltan keluaran. Selain itu, skim kawalan baru meminimumkan kehilangan pengaliran dengan mengurangkan purata arus induktor dan kehilangan pensuisan dengan menjadikan penukar beroperasi seperti penukar wang atau rangsangan. Model isyarat kecil penukar DC-DC step-up/step-down juga diperoleh untuk membimbing reka bentuk rangkaian pampasan. Penukar step-up/step-down direka dengan proses n-well CMOS 0.5 µm, dan boleh mengawal voltan keluaran dalam julat voltan masukan dari 2.5 V hingga 5.5 V dengan kecekapan kuasa maksimum 96%. Keputusan simulasi menunjukkan bahawa penukar yang dicadangkan mempamerkan voltan riak keluaran 28 mV dalam mod peralihan.
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Salinan
Yanzhao MA, Hongyi WANG, Guican CHEN, "Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 2, pp. 646-652, February 2011, doi: 10.1587/transfun.E94.A.646.
Abstract: This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.646/_p
Salinan
@ARTICLE{e94-a_2_646,
author={Yanzhao MA, Hongyi WANG, Guican CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition},
year={2011},
volume={E94-A},
number={2},
pages={646-652},
abstract={This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.},
keywords={},
doi={10.1587/transfun.E94.A.646},
ISSN={1745-1337},
month={February},}
Salinan
TY - JOUR
TI - Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 646
EP - 652
AU - Yanzhao MA
AU - Hongyi WANG
AU - Guican CHEN
PY - 2011
DO - 10.1587/transfun.E94.A.646
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2011
AB - This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.
ER -