The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan seni bina separa terlipat kerumitan rendah bagi penapis FIR tertranspos dan interpolator padu B-spline untuk sistem penyiaran daratan ATSC. Dengan menggunakan pemultipleks, penapis dan interpolator FIR yang dicadangkan boleh memberikan frekuensi jam yang tinggi dan kerumitan perkakasan yang rendah. Kaedah perwakilan binari digunakan untuk mereka bentuk penapis FIR peringkat tinggi. Juga, untuk mengimbangi ralat pemangkasan keluaran penapis FIR, kaedah pengesanan julat titik tetap telah digunakan. Seni bina separa berlipat yang dicadangkan telah direka bentuk dan dilaksanakan dengan teknologi CMOS 90-nm yang mempunyai voltan bekalan 1.1 V. Keputusan pelaksanaan menunjukkan bahawa seni bina yang dicadangkan mempunyai 12% dan 16% kurang kerumitan perkakasan daripada jenis seni bina yang lain. Juga, kedua-dua penapis dan interpolator beroperasi pada frekuensi jam masing-masing 200 MHz dan 385 MHz.
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Salinan
Yong-Kyu KIM, Chang-Seok CHOI, Hanho LEE, "Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 3, pp. 937-945, March 2011, doi: 10.1587/transfun.E94.A.937.
Abstract: This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.937/_p
Salinan
@ARTICLE{e94-a_3_937,
author={Yong-Kyu KIM, Chang-Seok CHOI, Hanho LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems},
year={2011},
volume={E94-A},
number={3},
pages={937-945},
abstract={This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively.},
keywords={},
doi={10.1587/transfun.E94.A.937},
ISSN={1745-1337},
month={March},}
Salinan
TY - JOUR
TI - Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 937
EP - 945
AU - Yong-Kyu KIM
AU - Chang-Seok CHOI
AU - Hanho LEE
PY - 2011
DO - 10.1587/transfun.E94.A.937
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2011
AB - This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively.
ER -