The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini mencadangkan seni bina pemultipleksan strim teragih untuk LSI codec video dengan konfigurasi berbilang cip. Seni bina teragih ini menggunakan unit pemultipleksan media terbina dalam dengan input aliran luaran dan antara muka komunikasi antara cip. Pemprosesan protokol selari, dengan mekanisme kawalan antara cip autonomi untuk mencampur dan menggabungkan paket melalui laluan pemindahan rantai daisy, menyediakan output aliran berbilang cip yang lengkap di penghujung rantai. Mendispens dengan peranti pasca pemprosesan luaran menyumbang kepada pemprosesan tinggi dan pengecilan sistem codec video mewah. Ia boleh dikonfigurasikan untuk pengekodan selari bagi video resolusi super tinggi, penglihatan HDTV berbilang pandangan/-bersudut dan berbilang program HDTV. Seni bina telah berjaya dilaksanakan dalam satu cip tunggal MPEG-2 422P@HL codec LSI dan digunakan untuk pembangunan sistem codec video resolusi super tinggi.
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Salinan
Takayuki ONISHI, Ken NAKAMURA, Takeshi YOSHITOME, Jiro NAGANUMA, "A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 12, pp. 2862-2867, December 2008, doi: 10.1093/ietisy/e91-d.12.2862.
Abstract: This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.12.2862/_p
Salinan
@ARTICLE{e91-d_12_2862,
author={Takayuki ONISHI, Ken NAKAMURA, Takeshi YOSHITOME, Jiro NAGANUMA, },
journal={IEICE TRANSACTIONS on Information},
title={A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV},
year={2008},
volume={E91-D},
number={12},
pages={2862-2867},
abstract={This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.},
keywords={},
doi={10.1093/ietisy/e91-d.12.2862},
ISSN={1745-1361},
month={December},}
Salinan
TY - JOUR
TI - A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV
T2 - IEICE TRANSACTIONS on Information
SP - 2862
EP - 2867
AU - Takayuki ONISHI
AU - Ken NAKAMURA
AU - Takeshi YOSHITOME
AU - Jiro NAGANUMA
PY - 2008
DO - 10.1093/ietisy/e91-d.12.2862
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2008
AB - This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.
ER -