The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pembalut standard IEEE 1500 memerlukan input dan outputnya disambungkan terus ke input dan output utama cip untuk kebolehkawalan dan pemerhatian. Ini biasanya dicapai dengan menyediakan Mekanisme Akses Ujian (TAM) khusus antara pembungkus dan input dan output utama. Walau bagaimanapun, apabila menggunakan semula sambung Rangkaian-pada-Cip (NoC) tertanam dan bukannya TAM khusus, pembungkus standard tidak boleh digunakan sebagaimana adanya kerana mekanisme pemindahan berasaskan paket dan keperluan fungsi lain oleh NoC. Dalam kertas ini, kami menerangkan dua pembungkus serasi NoC, yang mengatasi batasan pembungkus 1500 ini. Pembalut (Jenis 1 dan Jenis 2) saling melengkapi untuk mengoptimumkan penggunaan lebar jalur NoC sambil meminimumkan overhed kawasan. Pembalut Jenis 2 menggunakan overhed kawasan yang lebih besar untuk meningkatkan kecekapan lebar jalur, manakala Jenis 1 memanfaatkan beberapa konfigurasi khas yang mungkin tidak memerlukan pembalut yang kompleks dan kos tinggi. Dua algoritma pengoptimuman pembalut digunakan pada kedua-dua reka bentuk pembalut di bawah kekangan lebar jalur saluran dan masa ujian, menghasilkan peningkatan yang sangat sedikit atau tiada peningkatan dalam masa aplikasi ujian berbanding pendekatan TAM khusus konvensional.
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Salinan
Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Hideo FUJIWARA, "NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 7, pp. 2008-2017, July 2008, doi: 10.1093/ietisy/e91-d.7.2008.
Abstract: The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.7.2008/_p
Salinan
@ARTICLE{e91-d_7_2008,
author={Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints},
year={2008},
volume={E91-D},
number={7},
pages={2008-2017},
abstract={The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.},
keywords={},
doi={10.1093/ietisy/e91-d.7.2008},
ISSN={1745-1361},
month={July},}
Salinan
TY - JOUR
TI - NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
T2 - IEICE TRANSACTIONS on Information
SP - 2008
EP - 2017
AU - Fawnizu Azmadi HUSSIN
AU - Tomokazu YONEDA
AU - Hideo FUJIWARA
PY - 2008
DO - 10.1093/ietisy/e91-d.7.2008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2008
AB - The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.
ER -