The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami mempersembahkan cara yang sistematik dan cekap untuk mengurus memori metrik laluan dan memudahkan rangkaian sambungannya ke unit add_compare_select (ACSU) untuk reka bentuk penyahkod Viterbi (VD). Menggunakan persamaan terbitan untuk pembahagian memori dan susunan tambah-banding-pilih (ACS) bersama-sama dengan skim penjadualan di tempat lanjutan yang dicadangkan dalam kerja ini, kita boleh meningkatkan lebar jalur memori untuk akses metrik laluan bebas konflik dengan sambungan berwayar keras antara laluan memori metrik dan ACSU. Berbanding dengan kerja sedia ada, seni bina yang dibangunkan mempunyai kelebihan berikut: (1) Setiap bank memori yang dipisahkan boleh dianggap sebagai memori tempatan bagi elemen pemprosesan tertentu, di dalam ACSU, dengan sambungan berwayar keras, supaya kerumitan antara sambungan dikurangkan dengan ketara. . (2) Bank memori yang dipisahkan boleh digabungkan menjadi dua bank pseudo sahaja tanpa mengira bilangan elemen pemprosesan ACS yang diterima pakai. Ini bukan sahaja sangat memudahkan reka bentuk unit penjanaan alamat, tetapi juga menjadikan saiz fizikal memori yang diperlukan lebih kecil. (3) Pelaksanaan boleh dicapai dengan cara yang sistematik dengan litar kawalan biasa dan mudah. Keputusan eksperimen menunjukkan keberkesanan seni bina yang dibangunkan dan faedahnya akan lebih jelas untuk kod konvolusi dengan susunan memori yang besar.
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Salinan
Ming-Der SHIEH, Tai-Ping WANG, Chien-Ming WU, "Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 9, pp. 2300-2311, September 2008, doi: 10.1093/ietisy/e91-d.9.2300.
Abstract: We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.9.2300/_p
Salinan
@ARTICLE{e91-d_9_2300,
author={Ming-Der SHIEH, Tai-Ping WANG, Chien-Ming WU, },
journal={IEICE TRANSACTIONS on Information},
title={Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders},
year={2008},
volume={E91-D},
number={9},
pages={2300-2311},
abstract={We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.},
keywords={},
doi={10.1093/ietisy/e91-d.9.2300},
ISSN={1745-1361},
month={September},}
Salinan
TY - JOUR
TI - Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders
T2 - IEICE TRANSACTIONS on Information
SP - 2300
EP - 2311
AU - Ming-Der SHIEH
AU - Tai-Ping WANG
AU - Chien-Ming WU
PY - 2008
DO - 10.1093/ietisy/e91-d.9.2300
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2008
AB - We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.
ER -