The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas ini, skema cache arahan yang dipanggil Pengesanan Berbilang Laluan dicadangkan untuk meningkatkan cache jejak. Laluan diklasifikasikan untuk meningkatkan nisbah hit cache jejak dengan mengurangkan konflik laluan dan blok asas dicantumkan untuk mengurangkan kos perkakasan yang diperlukan untuk melaksanakan cache jejak. Keputusan simulasi untuk pelbagai penanda aras integer SPEC menunjukkan bahawa skim yang dicadangkan meningkatkan nisbah hit sebanyak lebih daripada 25% dan saiz pengambilan berkesan sebanyak 10%.
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Salinan
Jin-Hyuk YANG, In-Cheol PARK, Chong-Min KYUNG, "Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 10, pp. 1338-1343, October 1999, doi: .
Abstract: In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_10_1338/_p
Salinan
@ARTICLE{e82-d_10_1338,
author={Jin-Hyuk YANG, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Information},
title={Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors},
year={1999},
volume={E82-D},
number={10},
pages={1338-1343},
abstract={In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.},
keywords={},
doi={},
ISSN={},
month={October},}
Salinan
TY - JOUR
TI - Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
T2 - IEICE TRANSACTIONS on Information
SP - 1338
EP - 1343
AU - Jin-Hyuk YANG
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1999
AB - In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.
ER -