The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A. Chatterjee et al. ujian yang dicadangkan dengan sifat lineariti untuk kerosakan kelewatan get untuk menentukan, pada kelajuan jam yang diperlukan, sama ada litar yang sedang diuji adalah cip marginal atau tidak. Masa peralihan terkini pada output utama diubah secara linear dengan saiz kerosakan kelewatan get apabila ujian yang dicadangkan digunakan pada litar yang sedang diuji. Untuk pengetahuan pengarang, tiada laporan tentang kaedah algoritma untuk menjana ujian dengan sifat lineariti telah dibentangkan sebelum ini. Dalam makalah ini, kami mencadangkan satu kaedah untuk menjana ujian dengan sifat lineariti untuk kerosakan kelewatan get. Kaedah yang dicadangkan memperkenalkan kalkulus masa lanjutan baharu untuk mengira saiz kesalahan kelewatan get tertentu yang boleh disebarkan ke output utama. Kaedah ini telah digunakan pada litar penanda aras ISCAS di bawah model kelewatan unit.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, "A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 11, pp. 1466-1473, November 1999, doi: .
Abstract: A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_11_1466/_p
Salinan
@ARTICLE{e82-d_11_1466,
author={Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Information},
title={A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits},
year={1999},
volume={E82-D},
number={11},
pages={1466-1473},
abstract={A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1466
EP - 1473
AU - Hiroshi TAKAHASHI
AU - Kwame Osei BOATENG
AU - Yuzo TAKAMATSU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 1999
AB - A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
ER -