The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Transistor neuron-MOS (νMOS) digunakan pada litar logik berbilang nilai (MVL) mod semasa. Pertama, cermin arus νMOS baru voltan rendah dan kuasa rendah dibentangkan. Kemudian, pengesan ambang dan gerbang T kuaterner menggunakan cermin arus νMOS yang dicadangkan dicadangkan. Voltan keluaran minimum cermin arus νMOS dikurangkan sebanyak VT (voltan ambang), berbanding dengan cermin semasa cascode berganda konvensional. Pengesan ambang νMOS dibina pada pembanding arus νMOS yang asalnya terdiri daripada cermin semasa νMOS. Ia mempunyai ayunan keluaran yang tinggi dan ciri pemindahan yang tajam. Kecerunan keluaran pembanding yang dicadangkan di rantau pemindahan boleh ditingkatkan 6.3 kali ganda berbanding dengan kecerunan dalam pembanding konvensional. Bersama-sama dengan operasi pembanding arus novel yang lebih baik, keupayaan diskriminasi pengesan ambang νMOS yang dicadangkan juga meningkat. Prestasi litar yang dicadangkan disahkan oleh HSPICE dengan parameter peranti CMOS Motorola 1.5 µm. Tambahan pula, pengendalian cermin semasa νMOS juga disahkan melalui eksperimen pada cip ujian yang direka oleh VDEC*. Kawasan aktif cermin arus νMOS yang dicadangkan ialah 63 µm
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Salinan
Jing SHEN, Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, "Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 5, pp. 940-948, May 1999, doi: .
Abstract: A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_5_940/_p
Salinan
@ARTICLE{e82-d_5_940,
author={Jing SHEN, Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, },
journal={IEICE TRANSACTIONS on Information},
title={Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic},
year={1999},
volume={E82-D},
number={5},
pages={940-948},
abstract={A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm
keywords={},
doi={},
ISSN={},
month={May},}
Salinan
TY - JOUR
TI - Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic
T2 - IEICE TRANSACTIONS on Information
SP - 940
EP - 948
AU - Jing SHEN
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
AU - Zheng TANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 1999
AB - A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm
ER -