The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Seni bina mikro moden menggunakan teknik superscalar untuk meningkatkan prestasi sistem. Memandangkan mikropemproses superscalar mesti mengambil sekurang-kurangnya satu baris cache arahan pada satu masa untuk menyokong kadar keluaran yang tinggi dan pelaksanaan spekulatif dalam jumlah besar. Terdapat kes bahawa beberapa cawangan sering ditemui dalam satu kitaran. Dan dalam pelaksanaan praktikal ini akan menyebabkan masalah yang serius sementara terdapat pembolehubah bilangan alamat arahan yang mencari Penampan Sasaran Cawangan secara serentak. Dalam kertas kerja ini, kami mencadangkan Penampan Sasaran Cawangan Bersekutu Range (RABTB) yang boleh mengecam dan meramalkan berbilang cawangan dalam baris cache arahan yang sama untuk seni bina mikro isu luas. Beberapa konfigurasi RABTB disimulasikan dan dibandingkan menggunakan penanda aras SPECint95. Kami menunjukkan bahawa dengan saiz skop ramalan yang munasabah, ramalan cawangan boleh dipertingkatkan dengan menyokong berbilang / sehingga 8 ramalan cawangan dalam satu baris cache dalam satu kitaran. Keputusan simulasi kami menunjukkan bahawa RABTB yang optimum hendaklah 2048 entri, 8-lajur julat-bersekutu dan 8-masukan seni bina penimbal cincin diubah suai menggunakan algoritma ramalan PAs. Ia mempunyai purata 5.2 IPC_f dan penalti cawangan bagi setiap cawangan sebanyak 0.54 kitaran. Ini hampir dua kali lebih baik daripada mekanisme yang membuat ramalan hanya pada cawangan pertama yang ditemui.
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Salinan
Shu-Lin HWANG, Che-Chun CHEN, Feipei LAI, "Multiple Branch Prediction for Wide-Issue Superscalar" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 8, pp. 1154-1166, August 1999, doi: .
Abstract: Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while there are variable number of instruction addresses that look up the Branch Target Buffer simultaneously. In this paper, we propose a Range Associative Branch Target Buffer (RABTB) that can recognize and predict multiple branches in the same instruction cache line for a wide-issue micro-architecture. Several configurations of the RABTB are simulated and compared using the SPECint95 benchmarks. We show that with a reasonable size of prediction scope, branch prediction can be improved by supporting multiple / up to 8 branch predictions in one cache line in one cycle. Our simulation results show that the optimal RABTB should be 2048 entry, 8-column range-associate and 8-entry modified ring buffer architecture using PAs prediction algorithm. It has an average 5.2 IPC_f and branch penalty per branch of 0.54 cycles. This is almost two times better than a mechanism that makes prediction only on the first encountered branch.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_8_1154/_p
Salinan
@ARTICLE{e82-d_8_1154,
author={Shu-Lin HWANG, Che-Chun CHEN, Feipei LAI, },
journal={IEICE TRANSACTIONS on Information},
title={Multiple Branch Prediction for Wide-Issue Superscalar},
year={1999},
volume={E82-D},
number={8},
pages={1154-1166},
abstract={Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while there are variable number of instruction addresses that look up the Branch Target Buffer simultaneously. In this paper, we propose a Range Associative Branch Target Buffer (RABTB) that can recognize and predict multiple branches in the same instruction cache line for a wide-issue micro-architecture. Several configurations of the RABTB are simulated and compared using the SPECint95 benchmarks. We show that with a reasonable size of prediction scope, branch prediction can be improved by supporting multiple / up to 8 branch predictions in one cache line in one cycle. Our simulation results show that the optimal RABTB should be 2048 entry, 8-column range-associate and 8-entry modified ring buffer architecture using PAs prediction algorithm. It has an average 5.2 IPC_f and branch penalty per branch of 0.54 cycles. This is almost two times better than a mechanism that makes prediction only on the first encountered branch.},
keywords={},
doi={},
ISSN={},
month={August},}
Salinan
TY - JOUR
TI - Multiple Branch Prediction for Wide-Issue Superscalar
T2 - IEICE TRANSACTIONS on Information
SP - 1154
EP - 1166
AU - Shu-Lin HWANG
AU - Che-Chun CHEN
AU - Feipei LAI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 1999
AB - Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while there are variable number of instruction addresses that look up the Branch Target Buffer simultaneously. In this paper, we propose a Range Associative Branch Target Buffer (RABTB) that can recognize and predict multiple branches in the same instruction cache line for a wide-issue micro-architecture. Several configurations of the RABTB are simulated and compared using the SPECint95 benchmarks. We show that with a reasonable size of prediction scope, branch prediction can be improved by supporting multiple / up to 8 branch predictions in one cache line in one cycle. Our simulation results show that the optimal RABTB should be 2048 entry, 8-column range-associate and 8-entry modified ring buffer architecture using PAs prediction algorithm. It has an average 5.2 IPC_f and branch penalty per branch of 0.54 cycles. This is almost two times better than a mechanism that makes prediction only on the first encountered branch.
ER -