The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini menerangkan mikropemproses berasaskan seni bina baharu, pemproses selari boleh atur cara secara dinamik (DPPP), yang terdiri daripada sejumlah besar ALU dipermudah (sALU) sebagai blok pemprosesan. Semua sALU disambungkan melalui antara muka bas berbilang akses pembahagian kod yang menyediakan fleksibiliti penghalaan lengkap dengan mewujudkan sambungan secara maya melalui pemadanan kod dan bukannya wayar fizikal. Ciri ini digunakan lagi untuk mencapai keselarian tinggi dan toleransi kesalahan. Toleransi kesalahan yang tinggi direalisasikan tanpa batasan teknik berasaskan fabrikasi konvensional atau menyediakan elemen ganti. Satu lagi ciri DPPP ialah kebolehprogramannya yang mudah, kerana ia boleh dikonfigurasikan dengan menyusun input formula berangka menggunakan antara muka program auto pengguna yang disediakan. Cip prototaip berdasarkan seni bina yang dicadangkan telah dilaksanakan pada 4.5 mm
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Salinan
Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, "Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1521-1527, November 2001, doi: .
Abstract: This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1521/_p
Salinan
@ARTICLE{e84-d_11_1521,
author={Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface},
year={2001},
volume={E84-D},
number={11},
pages={1521-1527},
abstract={This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface
T2 - IEICE TRANSACTIONS on Information
SP - 1521
EP - 1527
AU - Boon-Keat TAN
AU - Ryuji YOSHIMURA
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
ER -