The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam beberapa tahun kebelakangan ini, logik domino telah mendapat banyak perhatian sebagai teknik reka bentuk litar berkelajuan tinggi. Walau bagaimanapun, dalam kes logik domino standard, hanya fungsi bukan penyongsangan dibenarkan. Kemudian, logik domino clock-delayed (CD) yang menyediakan sebarang fungsi logik dicadangkan untuk mengatasi kelemahan domino tersebut. Selain itu, litar domino lebih sensitif kepada bunyi litar berbanding litar CMOS statik. Khususnya, crosstalk menyebabkan masalah kritikal. Oleh itu, kami menumpukan perhatian kami pada kesilapan crosstalk dalam litar domino CD. Walau bagaimanapun, dalam litar domino CD, terdapat ralat yang tidak menyebarkan nilai yang rosak kepada mana-mana output utama walaupun denyutan crosstalk dijana. Kemudian, kami mengalih keluar ralat tersebut daripada senarai ralat sasaran dengan mempertimbangkan struktur litar domino CD, dan melakukan simulasi ralat untuk senarai ralat sasaran yang dikurangkan menggunakan dua jenis kaedah simulasi ralat bersama-sama. Kami menyedari litar domino CD dalam VHDL dan melaksanakan simulasi kerosakan yang dicadangkan untuk bahagian gabungan beberapa litar penanda aras ISCAS'89 pada simulator VHDL. Liputan kesalahan untuk vektor rawak diperolehi untuk s27 hingga s1494 di bawah had masa simulasi.
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Salinan
Kazuya SHIMIZU, Takanori SHIRAI, Masaya TAKAMURA, Noriyoshi ITAZAKI, Kozo KINOSHITA, "Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1526-1533, October 2002, doi: .
Abstract: In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1526/_p
Salinan
@ARTICLE{e85-d_10_1526,
author={Kazuya SHIMIZU, Takanori SHIRAI, Masaya TAKAMURA, Noriyoshi ITAZAKI, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits},
year={2002},
volume={E85-D},
number={10},
pages={1526-1533},
abstract={In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.},
keywords={},
doi={},
ISSN={},
month={October},}
Salinan
TY - JOUR
TI - Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1526
EP - 1533
AU - Kazuya SHIMIZU
AU - Takanori SHIRAI
AU - Masaya TAKAMURA
AU - Noriyoshi ITAZAKI
AU - Kozo KINOSHITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.
ER -