The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam makalah ini, seni bina VLSI untuk transformasi wavelet diskret berasaskan angkat (LDWT) dibentangkan. Seni bina kami melipat pengiraan semua tahap resolusi ke dalam unit laluan rendah dan laluan tinggi yang sama untuk mencapai penggunaan perkakasan yang lebih tinggi. Disebabkan oleh struktur reka bentuk yang tetap dan fleksibel, kawasannya adalah bebas daripada panjang jujukan input 1-D, dan kependamannya adalah bebas daripada bilangan tahap resolusi. Untuk pengiraan proses analisis bagi N-sampel LDWT 1-D 3 peringkat, reka bentuk kami mengambil masa lebih kurang N kitaran jam dan memerlukan 2 pengganda, 4 penambah dan 22 daftar. Ia direka dengan perpustakaan sel TSMC 0.35-µm dan mempunyai saiz cetakan 1.2
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Salinan
Pei-Yin CHEN, "VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 12, pp. 1893-1897, December 2002, doi: .
Abstract: In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_12_1893/_p
Salinan
@ARTICLE{e85-d_12_1893,
author={Pei-Yin CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter},
year={2002},
volume={E85-D},
number={12},
pages={1893-1897},
abstract={In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter
T2 - IEICE TRANSACTIONS on Information
SP - 1893
EP - 1897
AU - Pei-Yin CHEN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2002
AB - In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
ER -