The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam sistem pengkomputeran selari, rangkaian interkoneksi membentuk infrastruktur kritikal yang membolehkan komunikasi yang teguh dan berskala antara ratusan ribu nod. Rangkaian bertukar paket tradisional cenderung mengalami masa komunikasi yang panjang apabila kesesakan rangkaian berlaku. Dalam konteks ini, kami meneroka penggunaan pensuisan litar (CS) untuk menggantikan suis paket dengan perkakasan tersuai yang menyokong pensuisan berasaskan litar dengan cekap dengan kependaman rendah. Dalam rangkaian CS sasaran kami, jumlah lebar jalur tertentu dijamin untuk setiap pasangan komunikasi supaya kependaman rangkaian boleh diramalkan apabila bilangan pasangan nod yang terhad bertukar-tukar mesej. Bilangan slot masa yang diperuntukkan dalam setiap suis adalah faktor langsung yang mempengaruhi kependaman hujung ke hujung, dengan itu kami meningkatkan penggunaan slot dan membangunkan penjana topologi rangkaian untuk meminimumkan bilangan slot masa yang dioptimumkan untuk menyasarkan aplikasi yang corak komunikasinya boleh diramal. Dengan simulasi acara diskret kuantitatif, kami menggambarkan bahawa bilangan slot minimum yang diperlukan boleh dikurangkan kepada bilangan kecil dalam topologi yang dijana oleh metodologi reka bentuk kami sambil mengekalkan kos rangkaian 50% kurang daripada itu dalam topologi tori standard.
Yao HU
National Institute of Informatics
Michihiro KOIBUCHI
National Institute of Informatics
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Salinan
Yao HU, Michihiro KOIBUCHI, "Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 2, pp. 247-260, February 2019, doi: 10.1587/transinf.2018EDP7225.
Abstract: In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7225/_p
Salinan
@ARTICLE{e102-d_2_247,
author={Yao HU, Michihiro KOIBUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems},
year={2019},
volume={E102-D},
number={2},
pages={247-260},
abstract={In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.},
keywords={},
doi={10.1587/transinf.2018EDP7225},
ISSN={1745-1361},
month={February},}
Salinan
TY - JOUR
TI - Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems
T2 - IEICE TRANSACTIONS on Information
SP - 247
EP - 260
AU - Yao HU
AU - Michihiro KOIBUCHI
PY - 2019
DO - 10.1587/transinf.2018EDP7225
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2019
AB - In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.
ER -