The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kependaman dan penggunaan tenaga DRAM adalah kebimbangan serius kerana (1) kependaman tidak banyak bertambah baik selama beberapa dekad dan (2) mesin terkini mempunyai kapasiti memori utama yang besar. Kajian peringkat peranti mengurangkannya dengan memendekkan masa menunggu operasi dalaman DRAM supaya ia cepat selesai dan menggunakan lebih sedikit tenaga. Mengaplikasikan teknik ini secara agresif untuk mencapainya ingatan anggaran adalah satu hala tuju yang menjanjikan untuk mengurangkan lagi overhed, memandangkan banyak aplikasi pusat data hari ini sedikit sebanyak teguh untuk berubah-ubah. Untuk memajukan penyelidikan tentang memori anggaran, ia diperlukan untuk menilainya kesan kepada aplikasi supaya kedua-dua penyelidik dan bakal pengguna memori anggaran boleh menyiasat cara ia mempengaruhi aplikasi realistik. Walau bagaimanapun, simulator perkakasan terlalu lambat untuk menjalankan beban kerja berulang kali dengan parameter yang berbeza. Untuk tujuan ini, kami mencadangkan kaedah ringan untuk menilai kesan memori anggaran. Idea ini adalah untuk mengira bilangan operasi dalaman DRAM yang berlaku untuk menganggarkan data aplikasi dan mengira kebarangkalian bit-flip berdasarkannya, dan bukannya menggunakan simulator berat. Penilaian menunjukkan bahawa sistem kami adalah 3 susunan magnitud lebih pantas daripada simulator tepat kitaran, dan kami juga memberikan kajian kes menilai kesan memori anggaran kepada beberapa aplikasi yang realistik.
Soramichi AKIYAMA
The University of Tokyo
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Salinan
Soramichi AKIYAMA, "A Lightweight Method to Evaluate Effect of Approximate Memory with Hardware Performance Monitors" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 12, pp. 2354-2365, December 2019, doi: 10.1587/transinf.2019PAP0012.
Abstract: The latency and the energy consumption of DRAM are serious concerns because (1) the latency has not improved much for decades and (2) recent machines have huge capacity of main memory. Device-level studies reduce them by shortening the wait time of DRAM internal operations so that they finish fast and consume less energy. Applying these techniques aggressively to achieve approximate memory is a promising direction to further reduce the overhead, given that many data-center applications today are to some extent robust to bit-flips. To advance research on approximate memory, it is required to evaluate its effect to applications so that both researchers and potential users of approximate memory can investigate how it affects realistic applications. However, hardware simulators are too slow to run workloads repeatedly with different parameters. To this end, we propose a lightweight method to evaluate effect of approximate memory. The idea is to count the number of DRAM internal operations that occur to approximate data of applications and calculate the probability of bit-flips based on it, instead of using heavy-weight simulators. The evaluation shows that our system is 3 orders of magnitude faster than cycle accurate simulators, and we also give case studies of evaluating effect of approximate memory to some realistic applications.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2019PAP0012/_p
Salinan
@ARTICLE{e102-d_12_2354,
author={Soramichi AKIYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={A Lightweight Method to Evaluate Effect of Approximate Memory with Hardware Performance Monitors},
year={2019},
volume={E102-D},
number={12},
pages={2354-2365},
abstract={The latency and the energy consumption of DRAM are serious concerns because (1) the latency has not improved much for decades and (2) recent machines have huge capacity of main memory. Device-level studies reduce them by shortening the wait time of DRAM internal operations so that they finish fast and consume less energy. Applying these techniques aggressively to achieve approximate memory is a promising direction to further reduce the overhead, given that many data-center applications today are to some extent robust to bit-flips. To advance research on approximate memory, it is required to evaluate its effect to applications so that both researchers and potential users of approximate memory can investigate how it affects realistic applications. However, hardware simulators are too slow to run workloads repeatedly with different parameters. To this end, we propose a lightweight method to evaluate effect of approximate memory. The idea is to count the number of DRAM internal operations that occur to approximate data of applications and calculate the probability of bit-flips based on it, instead of using heavy-weight simulators. The evaluation shows that our system is 3 orders of magnitude faster than cycle accurate simulators, and we also give case studies of evaluating effect of approximate memory to some realistic applications.},
keywords={},
doi={10.1587/transinf.2019PAP0012},
ISSN={1745-1361},
month={December},}
Salinan
TY - JOUR
TI - A Lightweight Method to Evaluate Effect of Approximate Memory with Hardware Performance Monitors
T2 - IEICE TRANSACTIONS on Information
SP - 2354
EP - 2365
AU - Soramichi AKIYAMA
PY - 2019
DO - 10.1587/transinf.2019PAP0012
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2019
AB - The latency and the energy consumption of DRAM are serious concerns because (1) the latency has not improved much for decades and (2) recent machines have huge capacity of main memory. Device-level studies reduce them by shortening the wait time of DRAM internal operations so that they finish fast and consume less energy. Applying these techniques aggressively to achieve approximate memory is a promising direction to further reduce the overhead, given that many data-center applications today are to some extent robust to bit-flips. To advance research on approximate memory, it is required to evaluate its effect to applications so that both researchers and potential users of approximate memory can investigate how it affects realistic applications. However, hardware simulators are too slow to run workloads repeatedly with different parameters. To this end, we propose a lightweight method to evaluate effect of approximate memory. The idea is to count the number of DRAM internal operations that occur to approximate data of applications and calculate the probability of bit-flips based on it, instead of using heavy-weight simulators. The evaluation shows that our system is 3 orders of magnitude faster than cycle accurate simulators, and we also give case studies of evaluating effect of approximate memory to some realistic applications.
ER -