The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
RISC-V ialah seni bina set arahan terbuka dan bebas kesetiaan berasaskan RISC yang telah dibangunkan sejak 2010, dan boleh digunakan untuk pemproses lembut yang menjimatkan kos pada FPGA. Set arahan integer 32-bit asas dalam RISC-V ditakrifkan sebagai RV32I, yang mencukupi untuk menyokong persekitaran sistem pengendalian dan sesuai untuk sistem terbenam. Dalam kertas kerja ini, kami mencadangkan pemproses lembut RV32I yang dioptimumkan bernama RVCoreP yang menggunakan saluran paip lima peringkat. Tiga kaedah berkesan digunakan pada pemproses untuk meningkatkan kekerapan operasi. Kaedah ini ialah pengoptimuman unit pengambilan arahan, pengoptimuman ALU dan pengoptimuman memori data. Kami melaksanakan RVCoreP dalam Verilog HDL dan mengesahkan tingkah laku menggunakan simulasi Verilog dan papan FPGA Xilinx Atrix-7 sebenar. Kami menilai IPC (arahan setiap kitaran), kekerapan operasi, penggunaan sumber perkakasan dan prestasi pemproses. Daripada keputusan penilaian, kami menunjukkan bahawa RVCoreP mencapai 30.0% peningkatan prestasi berbanding dengan VexRiscv, iaitu pemproses RV32I berprestasi tinggi dan sumber terbuka yang dipilih daripada beberapa kerja berkaitan.
Hiromu MIYAZAKI
Tokyo Institute of Technology
Takuto KANAMORI
Tokyo Institute of Technology
Md Ashraful ISLAM
Tokyo Institute of Technology
Kenji KISE
Tokyo Institute of Technology
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Salinan
Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining" in IEICE TRANSACTIONS on Information,
vol. E103-D, no. 12, pp. 2494-2503, December 2020, doi: 10.1587/transinf.2020PAP0015.
Abstract: RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020PAP0015/_p
Salinan
@ARTICLE{e103-d_12_2494,
author={Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, },
journal={IEICE TRANSACTIONS on Information},
title={RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining},
year={2020},
volume={E103-D},
number={12},
pages={2494-2503},
abstract={RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.},
keywords={},
doi={10.1587/transinf.2020PAP0015},
ISSN={1745-1361},
month={December},}
Salinan
TY - JOUR
TI - RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
T2 - IEICE TRANSACTIONS on Information
SP - 2494
EP - 2503
AU - Hiromu MIYAZAKI
AU - Takuto KANAMORI
AU - Md Ashraful ISLAM
AU - Kenji KISE
PY - 2020
DO - 10.1587/transinf.2020PAP0015
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E103-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2020
AB - RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
ER -