The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Syarikat kereta telah cuba menggantikan cermin sisi kereta dengan kamera kecil untuk mengurangkan rintangan udara. Ia membolehkan kami menggunakan beberapa pemprosesan imej untuk meningkatkan kualiti imej. Contrast Limited Adaptive Histogram Equalization (CLAHE) ialah salah satu daripada teknik tersebut untuk meningkatkan kualiti imej bagi kamera cermin sisi, yang memerlukan prestasi pengiraan yang besar. Di sini, kaedah pelaksanaan CLAHE pada papan FPGA rendah melalui sintesis peringkat tinggi dicadangkan. CLAHE mempunyai dua bahagian pemprosesan utama: penjanaan fungsi pengedaran kumulatif (CDF), dan interpolasi dwilinear. Semasa penjanaan CDF, kesan peningkatan selang permulaan gelung boleh dikurangkan dengan banyaknya dengan meletakkan berbilang Elemen Pemprosesan (PE). dan semasa interpolasi, kependaman dan penggunaan BRAM telah dikurangkan dengan menyemak semula cara memegang CDF dan kaedah pengiraan. Akhir sekali, dengan menghubungkan setiap modul dengan antara muka penstriman, menggunakan pragma aliran data, pemprosesan bertindih dan menyembunyikan pemindahan data, pelaksanaan HLS kami mencapai hasil yang setanding dengan HDL. Kami membuat parameter komponen algoritma supaya bilangan jubin dan saiz imej boleh diubah dengan mudah. Kod sumber untuk penyelidikan ini boleh dimuat turun dari https://github.com/kokihonda/fpga_clahe.
Koki HONDA
Keio University
Kaijie WEI
Keio University
Masatoshi ARAI
Saitama University
Hideharu AMANO
Keio University
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Salinan
Koki HONDA, Kaijie WEI, Masatoshi ARAI, Hideharu AMANO, "CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis" in IEICE TRANSACTIONS on Information,
vol. E104-D, no. 12, pp. 2048-2056, December 2021, doi: 10.1587/transinf.2021PAP0006.
Abstract: Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2021PAP0006/_p
Salinan
@ARTICLE{e104-d_12_2048,
author={Koki HONDA, Kaijie WEI, Masatoshi ARAI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis},
year={2021},
volume={E104-D},
number={12},
pages={2048-2056},
abstract={Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.},
keywords={},
doi={10.1587/transinf.2021PAP0006},
ISSN={1745-1361},
month={December},}
Salinan
TY - JOUR
TI - CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis
T2 - IEICE TRANSACTIONS on Information
SP - 2048
EP - 2056
AU - Koki HONDA
AU - Kaijie WEI
AU - Masatoshi ARAI
AU - Hideharu AMANO
PY - 2021
DO - 10.1587/transinf.2021PAP0006
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E104-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2021
AB - Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.
ER -