The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cache peringkat terakhir (SLLC) yang dikongsi dalam berbilang pemproses cip jubin (TCMP) menyediakan kadar kehilangan cip luar yang rendah, tetapi ia menyebabkan kependaman akses pada cip yang panjang. Dalam hierarki cache dua peringkat, replikasi data menyimpan replika mangsa L1 dalam LLC tempatan (cache L2) untuk mendapatkan kependaman akses LLC tempatan yang singkat pada akses seterusnya. Banyak mekanisme replikasi data telah dicadangkan, tetapi mereka tidak menganggap kedua-dua gelagat guna semula mangsa L1 dan keupayaan penerimaan replika LLC. Mereka sama ada menghasilkan banyak replika yang tidak berguna atau meningkatkan tekanan LLC, yang mengehadkan peningkatan prestasi sistem. Dalam kertas kerja ini, kami mencadangkan a ttahap wo cache aware adaptif data rmekanisme eplikasi (TCDR), yang mengawal replikasi berdasarkan ramalan tingkah laku guna semula mangsa L1 dan pemantauan keupayaan penerimaan replika LLC. TCDR bukan sahaja meningkatkan ketepatan pemilihan replika L1, tetapi juga mengelakkan tekanan replikasi pada LLC. Keputusan menunjukkan bahawa TCDR meningkatkan prestasi sistem dengan overhed perkakasan yang munasabah.
Qianqian WU
Harbin Institute of Technology
Zhenzhou JI
Harbin Institute of Technology
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Salinan
Qianqian WU, Zhenzhou JI, "A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC" in IEICE TRANSACTIONS on Information,
vol. E105-D, no. 7, pp. 1320-1324, July 2022, doi: 10.1587/transinf.2022EDL8002.
Abstract: The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2022EDL8002/_p
Salinan
@ARTICLE{e105-d_7_1320,
author={Qianqian WU, Zhenzhou JI, },
journal={IEICE TRANSACTIONS on Information},
title={A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC},
year={2022},
volume={E105-D},
number={7},
pages={1320-1324},
abstract={The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.},
keywords={},
doi={10.1587/transinf.2022EDL8002},
ISSN={1745-1361},
month={July},}
Salinan
TY - JOUR
TI - A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC
T2 - IEICE TRANSACTIONS on Information
SP - 1320
EP - 1324
AU - Qianqian WU
AU - Zhenzhou JI
PY - 2022
DO - 10.1587/transinf.2022EDL8002
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E105-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2022
AB - The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.
ER -