The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Peranti Logik Boleh Aturcara (MPLD) berasaskan memori ialah jenis peranti boleh dikonfigurasikan semula baharu yang dibina menggunakan tatasusunan SRAM am dalam konfigurasi intersambung yang unik. Penyelidikan ini bertujuan untuk mencadangkan pendekatan untuk menjamin kebolehpercayaan jangka panjang MPLD, termasuk kaedah ujian untuk mengenal pasti kecacatan antara sambungan dalam tatasusunan SRAM semasa fasa pengeluaran dan teknik pemantauan kelewatan untuk mengesan kegagalan yang disebabkan oleh penuaan. Kaedah ujian yang dicadangkan mengkonfigurasi data konfigurasi ujian pra-jana ke dalam SRAM untuk mencipta laluan penyebaran ralat, menggunakan vektor berjalan-sifar/satu luaran untuk merangsang ralat dan mengenal pasti ralat pada port keluaran luaran. Kaedah pemantauan kelewatan yang dicadangkan mengkonfigurasi reka bentuk logik pengayun cincin novel ke dalam MPLD untuk mengukur variasi kelewatan apabila peranti sedang digunakan secara praktikal. Keputusan simulasi logik dengan suntikan kesalahan mengesahkan keberkesanan kaedah yang dicadangkan.
Xihong ZHOU
Ehime University
Senling WANG
Ehime University
Yoshinobu HIGAMI
Ehime University
Hiroshi TAKAHASHI
Ehime University
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Salinan
Xihong ZHOU, Senling WANG, Yoshinobu HIGAMI, Hiroshi TAKAHASHI, "Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device" in IEICE TRANSACTIONS on Information,
vol. E107-D, no. 1, pp. 60-71, January 2024, doi: 10.1587/transinf.2023EDP7101.
Abstract: Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023EDP7101/_p
Salinan
@ARTICLE{e107-d_1_60,
author={Xihong ZHOU, Senling WANG, Yoshinobu HIGAMI, Hiroshi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Information},
title={Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device},
year={2024},
volume={E107-D},
number={1},
pages={60-71},
abstract={Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.},
keywords={},
doi={10.1587/transinf.2023EDP7101},
ISSN={1745-1361},
month={January},}
Salinan
TY - JOUR
TI - Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device
T2 - IEICE TRANSACTIONS on Information
SP - 60
EP - 71
AU - Xihong ZHOU
AU - Senling WANG
AU - Yoshinobu HIGAMI
AU - Hiroshi TAKAHASHI
PY - 2024
DO - 10.1587/transinf.2023EDP7101
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E107-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2024
AB - Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.
ER -