The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pepijat menjadi tidak dapat dielakkan dalam reka bentuk litar bersepadu yang kompleks. Adalah penting untuk mengenal pasti pepijat secepat mungkin melalui nyahpepijat pasca silikon. Untuk nyahpepijat pasca silikon, kebolehmerhatian adalah salah satu cabaran terbesar. Mekanisme nyahpepijat berasaskan imbasan menyediakan pemerhatian yang tinggi dengan menggunakan semula rantai imbasan. Walau bagaimanapun, adalah tidak mungkin untuk mengimbas dump kitaran demi kitaran semasa pelaksanaan program kerana masa yang berlebihan diperlukan. Sebenarnya, tidak perlu mengimbas keadaan bebas ralat. Dalam kertas ini, kami memperkenalkan Tetingkap Suspek untuk menampung kitaran jam di mana pepijat dicetuskan. Kemudian, kami membentangkan pendekatan yang cekap untuk menentukan tetingkap suspek. Berdasarkan Tetingkap Suspect, kami mencadangkan mekanisme nyahpepijat baru untuk mengesan pepijat secara sementara dan ruang. Memandangkan pembuangan imbasan hanya diambil dalam tetingkap suspek dengan mekanisme yang dicadangkan, masa yang diperlukan untuk mengesan pepijat dikurangkan dengan banyak. Pendekatan dinilai menggunakan litar penanda aras ISCAS'89 dan ITC'99. Keputusan eksperimen menunjukkan bahawa mekanisme yang dicadangkan boleh mengurangkan masa nyahpepijat keseluruhan dengan ketara berbanding dengan mekanisme nyahpepijat berasaskan imbasan sambil mengekalkan kebolehmerhatian yang tinggi.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Jianliang GAO, Yinhe HAN, Xiaowei LI, "A Novel Post-Silicon Debug Mechanism Based on Suspect Window" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 5, pp. 1175-1185, May 2010, doi: 10.1587/transinf.E93.D.1175.
Abstract: Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1175/_p
Salinan
@ARTICLE{e93-d_5_1175,
author={Jianliang GAO, Yinhe HAN, Xiaowei LI, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel Post-Silicon Debug Mechanism Based on Suspect Window},
year={2010},
volume={E93-D},
number={5},
pages={1175-1185},
abstract={Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability.},
keywords={},
doi={10.1587/transinf.E93.D.1175},
ISSN={1745-1361},
month={May},}
Salinan
TY - JOUR
TI - A Novel Post-Silicon Debug Mechanism Based on Suspect Window
T2 - IEICE TRANSACTIONS on Information
SP - 1175
EP - 1185
AU - Jianliang GAO
AU - Yinhe HAN
AU - Xiaowei LI
PY - 2010
DO - 10.1587/transinf.E93.D.1175
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2010
AB - Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability.
ER -