The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Maklumat tentang laluan palsu dalam litar berguna untuk reka bentuk dan ujian. Penggunaan maklumat ini boleh menyumbang bukan sahaja untuk mengurangkan kawasan litar, masa yang diperlukan untuk sintesis logik, penjanaan ujian dan aplikasi ujian litar, tetapi juga untuk mengurangkan ujian berlebihan. Memandangkan pengecaman laluan palsu pada aras pintu adalah sukar, beberapa kaedah menggunakan maklumat reka bentuk peringkat tinggi telah dicadangkan. Kaedah ini berkesan hanya jika surat-menyurat antara laluan di peringkat pemindahan daftar (RTL) dan di peringkat pintu boleh diwujudkan. Sehingga kini, memberikan sekatan pada sintesis logik adalah satu-satunya cara untuk mewujudkan surat-menyurat. Walau bagaimanapun, ia tidak praktikal untuk reka bentuk perindustrian. Dalam makalah ini, kami mencadangkan kaedah untuk memetakan laluan palsu RTL ke laluan tahap get yang sepadan tanpa sintesis logik tertentu; ia menjamin bahawa laluan aras get yang sepadan adalah palsu. Keputusan eksperimen menunjukkan bahawa kaedah pemetaan laluan kami boleh mewujudkan korespondensi laluan palsu RTL dan banyak laluan palsu peringkat get.
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Salinan
Hiroshi IWATA, Satoshi OHTAKE, Hideo FUJIWARA, "A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 7, pp. 1857-1865, July 2010, doi: 10.1587/transinf.E93.D.1857.
Abstract: Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1857/_p
Salinan
@ARTICLE{e93-d_7_1857,
author={Hiroshi IWATA, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification},
year={2010},
volume={E93-D},
number={7},
pages={1857-1865},
abstract={Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.},
keywords={},
doi={10.1587/transinf.E93.D.1857},
ISSN={1745-1361},
month={July},}
Salinan
TY - JOUR
TI - A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
T2 - IEICE TRANSACTIONS on Information
SP - 1857
EP - 1865
AU - Hiroshi IWATA
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2010
DO - 10.1587/transinf.E93.D.1857
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2010
AB - Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.
ER -