The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan seni bina Sistem pada Cip (SOC) berkuasa rendah untuk Bluetooth v2.0+EDR (Kadar Data Dipertingkat) dan aplikasinya. Reka bentuk kami termasuk pengawal pautan, modem, transceiver RF, Codec Sub-Band (SBC), Pemproses Set Komputer Arahan Diperluas (ESIC) dan perkakasan. Untuk mengurangkan penggunaan kuasa SOC yang dicadangkan, kami mengurangkan pemindahan data menggunakan memori dwi-port, termasuk unit pengurusan kuasa dan pendekatan berpagar jam. Kami juga menangani beberapa isu dan faedah persekitaran boleh guna semula dan bersatu pada struktur data terpusat dan platform pengesahan SOC. Ini termasuk fleksibiliti dalam memenuhi keperluan akhir menggunakan alat bebas teknologi di mana mungkin dalam pelbagai proses dan untuk projek. Matlamat lain kerja ini adalah untuk meminimumkan usaha reka bentuk dengan mengelakkan kerja yang sama dilakukan dua kali oleh orang yang berbeza dan untuk menggunakan semula persekitaran dan platform yang sama untuk projek yang berbeza. Cip ini menduduki saiz dadu 30 mm2 dalam 0.18 µm CMOS, dan arus kes terburuk daripada jumlah cip ialah 54 mA.
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Salinan
Jeonghun KIM, Suki KIM, Kwang-Hyun BAEK, "A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 9, pp. 2500-2508, September 2010, doi: 10.1587/transinf.E93.D.2500.
Abstract: This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2500/_p
Salinan
@ARTICLE{e93-d_9_2500,
author={Jeonghun KIM, Suki KIM, Kwang-Hyun BAEK, },
journal={IEICE TRANSACTIONS on Information},
title={A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform},
year={2010},
volume={E93-D},
number={9},
pages={2500-2508},
abstract={This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.},
keywords={},
doi={10.1587/transinf.E93.D.2500},
ISSN={1745-1361},
month={September},}
Salinan
TY - JOUR
TI - A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
T2 - IEICE TRANSACTIONS on Information
SP - 2500
EP - 2508
AU - Jeonghun KIM
AU - Suki KIM
AU - Kwang-Hyun BAEK
PY - 2010
DO - 10.1587/transinf.E93.D.2500
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2010
AB - This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.
ER -