The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini memperkenalkan Simulator ketepatan kitaran untuk Sistem MUlti-media boleh dikonfigurasikan semula secara dinamik, dipanggil SimREMUS. SimREMUS boleh sama ada digunakan pada peringkat transaksi, yang membolehkan pemodelan dan simulasi perkakasan peringkat tinggi dan perisian terbenam, atau pada peringkat pemindahan daftar, jika tingkah laku sistem dinamik dikehendaki diperhatikan pada tahap isyarat. Tukar ganti antara satu set kriteria yang kerap digunakan untuk mencirikan reka bentuk sistem pengkomputeran boleh dikonfigurasikan semula, seperti kebutiran, kebolehprograman, kebolehkonfigurasian serta seni bina elemen pemprosesan dan modul laluan dsb., boleh dinilai dengan cepat. Selain itu, rangkaian alat lengkap untuk SimREMUS, termasuk pengkompil dan penyahpepijat, dibangunkan. SimREMUS boleh mensimulasikan 270 k kitaran sesaat untuk juta gerbang SoC (System-on-a-Chip) dan menghasilkan satu bingkai H.264 1080p dalam masa 15 minit, yang mungkin memakan masa beberapa hari pada VCS (platform: CPU: E5200@ 2.5 Ghz, RAM : 2.0 GB). Simulasi menunjukkan bahawa 1080p@30 fps H.264 Profil Tinggi@ Tahap 4 boleh dicapai apabila mengeksploitasi frekuensi kerja 200 MHz pada seni bina VLSI REMUS.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, "A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 12, pp. 3202-3210, December 2010, doi: 10.1587/transinf.E93.D.3202.
Abstract: This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.3202/_p
Salinan
@ARTICLE{e93-d_12_3202,
author={Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System},
year={2010},
volume={E93-D},
number={12},
pages={3202-3210},
abstract={This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.},
keywords={},
doi={10.1587/transinf.E93.D.3202},
ISSN={1745-1361},
month={December},}
Salinan
TY - JOUR
TI - A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
T2 - IEICE TRANSACTIONS on Information
SP - 3202
EP - 3210
AU - Min ZHU
AU - Leibo LIU
AU - Shouyi YIN
AU - Chongyong YIN
AU - Shaojun WEI
PY - 2010
DO - 10.1587/transinf.E93.D.3202
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2010
AB - This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
ER -