The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan reka bentuk TLB (Penimbal Tepi Ketepi Terjemahan) data cekap kebocoran untuk pemproses terbenam. Disebabkan lokaliti data dalam program, rujukan TLB data cenderung untuk memukul hanya sebilangan kecil halaman semasa selang pelaksanaan yang singkat. Selepas membahagikan keseluruhan masa pelaksanaan kepada kepingan masa yang lebih kecil, mekanisme pengurangan kebocoran dicadangkan untuk mengesan entri TLB yang sebenarnya berfungsi untuk terjemahan alamat maya-ke-fizikal dalam setiap kepingan masa. Oleh itu, dengan penyepaduan teknik bekalan voltan dwi, entri TLB yang tidak digunakan untuk terjemahan alamat boleh dimasukkan ke dalam mod kebocoran rendah (dengan bekalan voltan rendah) untuk menjimatkan kuasa. Keputusan penilaian dengan lapan program MiBench menunjukkan bahawa reka bentuk yang dicadangkan boleh mengurangkan kuasa kebocoran data TLB sebanyak 37% secara purata, dengan penurunan prestasi kurang daripada 0.01%.
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Salinan
Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, "A Leakage Efficient Data TLB Design for Embedded Processors" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 1, pp. 51-59, January 2011, doi: 10.1587/transinf.E94.D.51.
Abstract: This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.51/_p
Salinan
@ARTICLE{e94-d_1_51,
author={Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Leakage Efficient Data TLB Design for Embedded Processors},
year={2011},
volume={E94-D},
number={1},
pages={51-59},
abstract={This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.},
keywords={},
doi={10.1587/transinf.E94.D.51},
ISSN={1745-1361},
month={January},}
Salinan
TY - JOUR
TI - A Leakage Efficient Data TLB Design for Embedded Processors
T2 - IEICE TRANSACTIONS on Information
SP - 51
EP - 59
AU - Zhao LEI
AU - Hui XU
AU - Daisuke IKEBUCHI
AU - Tetsuya SUNATA
AU - Mitaro NAMIKI
AU - Hideharu AMANO
PY - 2011
DO - 10.1587/transinf.E94.D.51
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2011
AB - This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
ER -